1. Field of the Invention
The present invention relates to an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver. More particularly, the present invention relates to an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of automatically controlling an identification level or an identification timing according to an input signal.
2. Description of the Related Art
In a high-speed long-distance optical transmission, an optical signal is subject to a waveform distortion due to characteristics of a fiber (e.g., a band reduction, a non-linear effect). Therefore, the optimal position of the identification level for the optical signal is constantly changing. At present, however, since the identification level is fixed to a single point, the identification level is not set to the optimal identification level for various conditions. A resulting drawback is a narrow error margin which may limit the transmission distance.
In view of such a problem in the prior art, methods for controlling an identification level or an identification phase have been proposed in the art.
For example, Japanese Laid-Open Patent Publication No. 08-265375 discloses a method for controlling an identification level and a method for controlling an identification phase. In the method for controlling the identification level, a comparison is made between two output signals of adjacent levels among three output signals from three identifiers which receive a data input and have respectively different identification levels (i.e., low, intermediate and high levels). For example, the high level output signal is compared with respect to the intermediate level output signal. If the comparison result indicates a mismatch, the three identification levels are parallelly (i.e., with the intervals therebetween kept unchanged) shifted toward a direction opposite to the identification level used in the comparison (e.g., the high level). For example, if a result indicating a mismatch occurred between the intermediate level and the high level, the three identification levels are parallelly shifted to lower levels, respectively. In the method for controlling the identification phase disclosed in this laid-open patent publication, a comparison is made between two output signals of adjacent timings among three output signals from three identifiers which receive a data input and have respectively different identification timings (i.e., delayed, intermediate and advanced phases). For example, the advanced phase output signal is compared with respect to the intermediate phase output signal. If the comparison result indicates a mismatch, the three identification timings are parallelly shifted toward a direction opposite to the identification timing used in the comparison (e.g., the advanced phase). For example, if a result indicating a mismatch occurred between the intermediate phase and the advanced phase, the three identification timings are parallelly shifted to more delayed timings, respectively.
However, the above-described conventional method has the following problems.
In the method for controlling an identification level or an identification phase described in Japanese Laid-Open Patent Publication No. 08-265375, supra, although all of the three identification levels or identification timings used for the control are parallelly shifted, the intervals therebetween are fixed. Therefore, the control system may be instable when the difference between high and low levels of the incoming signal decreases. Specifically, when the high identification level of the three identification levels is optimized, the low identification level may become less than the low level of the signal, resulting in a xe2x80x9cmismatchxe2x80x9d result from a comparison with respect to the output of the identifier of the intermediate identification level. Then, if the low identification level is optimized, the high identification level deviates from the optimal value. Therefore, the control system as a whole may not reach a stable state, whereby even an oscillation may occur.
An object of the present invention is to solve the above-described problem by providing an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of stably setting an identification level or an identification phase.
In order to achieve the above-described object, an automatic identification level control circuit of the present invention comprises: a plurality of identification circuits receiving an input data signal and having identification levels different from one another; a plurality of exclusive OR circuits each outputting a match determination signal indicating xe2x80x9cmatchxe2x80x9d or xe2x80x9cmismatchxe2x80x9d between outputs from the identification circuits which respectively correspond to two identification levels adjacent to each other in terms of magnitude among the identification levels different from one another; and an identification voltage control circuit for outputting a control signal for adjusting respective absolute values of the identification levels different from one another and an interval therebetween so that the match determination signal indicates xe2x80x9cmatchxe2x80x9d.
An automatic identification level control circuit of the present invention may comprise: a plurality of identification circuits receiving an input data signal and having identification levels different from one another; a plurality of exclusive OR circuits each outputting a match determination signal indicating xe2x80x9cmatchxe2x80x9d or xe2x80x9cmismatchxe2x80x9d between outputs from the identification circuits which respectively correspond to two identification levels adjacent to each other in terms of magnitude among the identification levels different from one another; and an identification voltage control circuit for outputting a control signal for adjusting a difference between a DC level of the input data signal and one of the identification levels different from one another, and each of the other identification levels so that the match determination signal indicates xe2x80x9cmatchxe2x80x9d.
The identification voltage control circuit may comprise: a charging circuit whose output voltage is incremented when a first one of the match determination signals corresponding to a first one of the identification levels indicates xe2x80x9cmismatchxe2x80x9d; a discharging circuit whose output voltage is decremented when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates xe2x80x9cmismatchxe2x80x9d; and a charging/discharging circuit having a first output whose voltage rapidly decreases when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually increases when both of the first and second match determination signals indicate xe2x80x9cmatchxe2x80x9d, and a second output whose voltage rapidly increases when at least one of the match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually decreases when both of the match determination signals indicate xe2x80x9cmatchxe2x80x9d.
The identification voltage control circuit may comprise: a discharging circuit whose output voltage is decremented when a first one of the match determination signals corresponding to a first one of the identification levels indicates xe2x80x9cmismatchxe2x80x9d; a charging circuit whose output voltage is incremented when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates xe2x80x9cmismatchxe2x80x9d; and a charging/discharging circuit having a first output whose voltage rapidly decreases when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually increases when both of the first and second match determination signals indicate xe2x80x9cmatchxe2x80x9d, and a second output whose voltage rapidly increases when at least one of the match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually decreases when both of the match determination signals indicate xe2x80x9cmatchxe2x80x9d.
The identification voltage control circuit may comprise: a first up/down counter which counts up when a first one of the match determination signals corresponding to a first one of the identification levels indicates xe2x80x9cmismatchxe2x80x9d and counts down when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates xe2x80x9cmismatchxe2x80x9d; a timer for providing a predetermined timing; a second up/down counter which counts down when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts up in accordance with the predetermined timing provided by the timer; and a third up/down counter which counts up when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts down in accordance with the predetermined timing provided by the timer.
The identification voltage control circuit may comprise: a first up/down counter which counts down when a first one of the match determination signals corresponding to a first one of the identification levels indicates xe2x80x9cmismatchxe2x80x9d and counts up when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates xe2x80x9cmismatchxe2x80x9d; a timer for providing a predetermined timing; a second up/down counter which counts down when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts up in accordance with the predetermined timing provided by the timer; and a third up/down counter which counts up when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts down in accordance with the predetermined timing provided by the timer.
The identification voltage control circuit may comprise: a discharging circuit whose output voltage is decremented when a first one of the match determination signals corresponding to a first one of the identification levels indicates xe2x80x9cmismatchxe2x80x9d; and a charging circuit whose output voltage is incremented when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates xe2x80x9cmismatchxe2x80x9d.
An average value between identification levels which respectively have a maximum value and a minimum value among the identification levels different from one another may be included as an identification level.
The automatic identification level control circuit may further comprise: a pulse width elongation circuit which is inserted between each of the plurality of exclusive OR circuits and the identification voltage control circuit for elongating the match determination signal.
An automatic identification phase control circuit of the present invention comprises: a plurality of identification circuits receiving an input data signal and having identification timings different from one another; a plurality of exclusive OR circuits each outputting a match determination signal indicating xe2x80x9cmatchxe2x80x9d or xe2x80x9cmismatchxe2x80x9d between outputs from the identification circuits which respectively correspond to two identification timings adjacent to each other in terms of delay amount among the identification timings different from one another; and an identification timing control circuit for outputting a control signal for adjusting respective ones of the identification timings different from one another so that the match determination signal indicates xe2x80x9cmatchxe2x80x9d.
The identification timing control circuit may comprise: a discharging circuit whose output voltage is decremented when a first one of the match determination signals corresponding to a first one of the identification timings indicates xe2x80x9cmismatchxe2x80x9d; a charging circuit whose output voltage is incremented when a second one of the match determination signals corresponding to a second one of the identification timings which is delayed with respect to the first identification timing indicates xe2x80x9cmismatchxe2x80x9d; and a charging/discharging circuit having a first output whose voltage rapidly decreases when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually increases when both of the match determination signals indicate xe2x80x9cmatchxe2x80x9d, and a second output whose voltage rapidly increases when at least one of the match determination signals indicates xe2x80x9cmismatchxe2x80x9d and gradually decreases when both of the match determination signals indicate xe2x80x9cmatchxe2x80x9d.
The identification timing control circuit may comprise: a first up/down counter which counts down when a first one of the match determination signals corresponding to a first one of the identification timings indicates xe2x80x9cmismatchxe2x80x9d and counts up when a second one of the match determination signals corresponding to a second one of the identification timings which is delayed with respect to the first identification timing indicates xe2x80x9cmismatchxe2x80x9d; a timer for providing a predetermined timing; a second up/down counter which counts down when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts up in accordance with the predetermined timing provided by the timer; and a third up/down counter which counts up when at least one of the first and second match determination signals indicates xe2x80x9cmismatchxe2x80x9d and counts down in accordance with the predetermined timing provided by the timer.
The identification timing control circuit may comprise: a discharging circuit whose output voltage is decremented when a first one of the match determination signals corresponding to a first one of the identification timings indicates xe2x80x9cmismatchxe2x80x9d; and a charging circuit whose output voltage is incremented when a second one of the match determination signals corresponding to a second one of the identification timings which is delayed with respect to the first identification timing indicates xe2x80x9cmismatchxe2x80x9d.
An average value between identification timings which respectively have a maximum delay amount and a minimum delay amount among the identification timings different from one another may be included as an identification timing.
The automatic identification phase control circuit may further comprise: a pulse width elongation circuit which is inserted between each of the plurality of exclusive OR circuits and the identification timing control circuit for elongating the match determination signal.
An identification level control method of the present invention comprises: an identification step of making a comparison in magnitude between an input data signal and each of a plurality of identification levels different from one another; a comparison step of making a comparison between comparison results from the identification step which respectively correspond to two of the identification levels different from one another, thereby giving a determination result of xe2x80x9cmatchxe2x80x9d or xe2x80x9cmismatchxe2x80x9d; and an identification voltage adjustment step of adjusting respective absolute values of the identification levels and an interval therebetween based on the determination result given in the comparison step.
The number of the identification levels may be three.
The identification voltage adjustment step may comprise: an identification level position adjustment step of shifting, by a same level, respective ones of the plurality of identification levels; and an identification level interval adjustment step of adjusting an interval between each pair of the plurality of identification levels.
The identification voltage adjustment step may comprise: an extreme identification level adjustment step of independently adjusting identification levels which respectively have a maximum value and a minimum value among the plurality of identification levels; and an intermediate identification level setting step of setting a value of each remaining identification level to a value which divides, at a predetermined division ratio, a voltage level range between the identification levels which respectively have the maximum value and the minimum value.
The identification level control method may further comprise: an interval widening step of gradually widening a difference between identification levels which respectively have a maximum value and a minimum value among the identification levels during a time period in which the comparison step is giving a determination result of xe2x80x9cmatchxe2x80x9d.
The identification level control method may comprise: an identification step of producing an identification output obtained by making a comparison in magnitude between an input digital signal and a predetermined identification level; an error detection step of detecting an error in a code string which forms the identification output; and an identification level changing step of increasing the identification level when a low level is erroneously identified as a high level, and decreasing the identification level when a high level is erroneously identified as a low level.
An identification phase control method of the present invention comprises: an identification step of producing a plurality of identification outputs each obtained by making a comparison in magnitude between an input digital signal and a predetermined identification level with a respective one of a plurality of identification timings different from one another; a comparison step of making a comparison between identification outputs from the identification step which respectively correspond to two of the plurality of identification timings, thereby giving a determination result of xe2x80x9cmatchxe2x80x9d or xe2x80x9cmismatchxe2x80x9d; and an identification timing adjustment step of adjusting the identification timings based on the determination result given in the comparison step.
The identification timing adjustment step may comprise: an identification timing position adjustment step of shifting, by a same level, respective ones of the plurality of identification timings; and an identification timing interval adjustment step of adjusting an interval between each pair of the plurality of identification timings.
The identification timing adjustment step may comprise: an extreme identification timing adjustment step of independently adjusting identification timings which respectively have a maximum delay amount and a minimum delay amount among the plurality of identification timings; and an intermediate identification timing setting step of setting a value of each remaining identification timing to a value which divides, at a predetermined division ratio, an identification timing range between the identification timings which respectively have the maximum delay amount and the minimum delay amount.
The identification phase control method further may comprise: an interval widening step of gradually widening a difference in delay amount between identification timings which respectively have a maximum delay amount and a minimum delay amount among the identification timings during a time period in which the comparison step is giving a determination result of xe2x80x9cmatchxe2x80x9d.
An optical receiver of the present invention comprises: a photodetector for converting an input optical signal into an electric signal; an automatic identification level control circuit as described above which receives the electric signal; and a clock extraction circuit for extracting and outputting a clock signal contained in the electric signal, and providing the extracted clock signal to the automatic identification level control circuit.
The optical receiver may further comprise: an identifier for receiving the electric signal and identifying the received electric signal based on one of the plurality of identification levels which has a value in a vicinity of a median among the plurality of identification levels, and a timing of the clock signal.
The optical receiver may further comprise: a capacitor inserted between the photodetector and the identifier.
The optical receiver may further comprise: an identification phase control circuit as described above, wherein the electric signal is input to the identification phase control circuit, one of the plurality of identification timings which has a delay amount in a vicinity of a median among the plurality of identification timings is provided to the automatic identification level control circuit, and one of the plurality of identification levels which has a value in a vicinity of a median among the plurality of identification levels is provided to the automatic identification phase control circuit.